Semiconductor devices formed in the surface region of a silicon wafer substrate each have multiple elements to be electrically connected to the surrounding circuitry and to each other. Some of these electrical connections extend through protective insulating layers that cover each device level to electrically isolate adjacent levels. The insulating layers typically provide planarized surfaces for subsequent semiconductor device fabrication. Insulating materials include borophosphosilicate glass (BPSG), oxide deposited from tetraethyl-orthosilicate (TEOS), newer low dielectric (low k) materials, etc.
For example, a memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) electrically connected to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET applies or removes charge on the capacitor, thus affecting the logical state defined by the memory cell. After formation of the MOSFET device elements, a protective insulating layer of BPSG is typically deposited, through which electrical connection must then be made to the subsequently fabricated capacitors and wiring layers above the BPSG layer. It is important to maintain good ohmic electrical connections between the capacitors and the underlying device elements (e.g., drain region of a MOSFET), and to maintain these good ohmic contacts throughout the lifetimes of the integrated circuits. Moreover, the material that contacts the substrate must be compatible so as not to poison the active areas and disturb finely tailored electrical characteristics.
Typically, vertical connections are made by filling vias formed through insulating layers with conductive polycrystalline silicon (i.e., polysilicon or poly), thereby contacting the substrate. The resultant structure filling the via is often referred to as a “poly plug.”
In order to maintain a certain minimum charge storage as device dimensions are scaled down and packing densities increase, capacitors for DRAM devices are being developed for incorporation of dielectric materials having increased dielectric constants (k). Such high k materials include tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT) and strontium bismuth tantalate (SBT). These materials are characterized by effective dielectric constants significantly higher than conventional dielectrics (e.g., silicon oxides and nitrides). Whereas k equals about 3.9 for silicon dioxide, the dielectric constants of these new materials can range from 20 to 40 (tantalum oxide) to 300 (BST), and some even higher (600 to 800). Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by future circuit design.
Difficulties have been encountered, however, in incorporating these materials into fabrication process flows. For example, Ta2O5 is deposited by chemical vapor deposition (CVD) employing organometallic precursors in a highly oxidizing ambient. Additionally, after deposition the material is annealed to remove carbon. This anneal is typically conducted in the presence of nitrous oxide (N2O), which is also highly oxidizing, while volatile carbon complexes are driven out.
Due to the oxidizing nature of the reactants and by-products for forming high-k materials, surrounding materials are subject to degradation. Similarly, formation of other high k materials often involves exposing adjacent materials to oxidizing or otherwise corrosive environments. Corrosion of the conductive materials forming the electrical connections to device elements reduces their conductivity, and has been viewed as a major obstacle to incorporating high-k materials into integrated circuits.
Accordingly, a need exists for improved contact plugs and methods of making the same.